1. Field of the Invention
This invention relates to cover slices for use in annealing of gallium arsenide wafers and other group III-V compounds, such as indium phosphide and, more specifically, to the use of a gallium arsenide or other group III-V compound cover for the wafer for entrapping volatilized arsenic therebetween, the material of the cover and the slice preferably being the same.
2. Brief Description of the Prior Art
It is known that, in the production of gallium arsenide FETs, it is normal to utilize a step of ion implantation. When this step is utilized, it is also necessary to utilize an annealing step. During the annealing of gallium arsenide wafers, the annealing temperature of 850 degrees C. is sufficiently high to cause the arsenic in the wafer to volatilize or outdiffuse as the annealing temperature is approached and thereby cause a degradation of the wafer surface due to the loss of arsenic therefrom. In order to avoid or minimize this problem, the prior art has utilized an overcoat over the wafer surface, such as silicon oxide or silicon nitride. This procedure has a number of problems, such as stressing of the wafer, peeling, diffusion of the coating constituents into the wafer as well as the requirement of the extra processing step.
The prior art has also attempted to overcome the above noted problem by the "proximity" method wherein two gallium arsenide wafers are placed face to face. When the opposing surfaces are polished, there is a tendency for these opposing surfaces to undergo liquid phase epitaxy and grow together, thereby ruining the wafers. This problem was overcome by placing a rough surface next to the polished surface. However, with the desire for even better surfaces and with the requirement that annealing take place after a pattern has been formed in the wafer surface, it became essential that the surfaces not make physical contact due to scarring and deposition of particles on the surface. This eliminated the "proximity" method as a viable option.